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1 ? fn6500.1 ISL8501 triple output controller with 1a standard buck pwm and dual ldos the ISL8501 is a high-performance, triple output controller that provides a single, high frequency power solution for a variety of point of load applicat ions. the ISL8501 integrates a 1a standard buck pwm contro ller and switching mosfet with two 500ma ldos. the pwm controller in the ISL8501 drives an internal switching n-channel power mosfet and requires an external schottky diode to ge nerate an output voltage from 0.6v to 20v. the integrated power switch is optimized for excellent thermal performance up to 1a of output current. the standard buck input voltage range supports a fixed 5v or variable 6v to 25v range. the pwm regulator switches at a fixed frequency of 500khz and utilizes simple voltage mode control with input voltage feed forward to provide flexibility in component selection and minimize solution size. protection features include overcurrent, undervoltage, and thermal overload protection in tegrated into the ic. the ISL8501 power good signal output indicates loss of regulation on the pwm output. the ISL8501 features two adj ustable ldo regulators using internal pmos transistors as pass devices. separate enable pins (en_ldo1, en_ldo2) control each ldo output. a single power good signal output indicates loss of regulation on either of the two ldo outputs. independent overcurrent and thermal fault shutdown moni tors are integrated into the ldo section. ISL8501 is available in a small 4mmx4mm quad flat no- lead (qfn) package. features ? standard buck controller with integrated switching power mosfet and dual ldos ? integrated boot diode ? input voltage range - fixed 5v 10% - variable 6v to 25v ? pwm output voltage adjustable from 0.6v to 20v with continuous output current up to 1a ? voltage mode control with voltage feed forward ? fixed 500khz switching frequency ? externally adjustable soft-start time ? output undervoltage protection ? dual ldo adjustable options - ldo1, 0.6v to 4.2v . . . . . . . . . . . . . . . . . . . . . . 500ma - ldo2, 0.6v to 4.2v . . . . . . . . . . . . . . . . . . . . . . 500ma ? individual enable inputs ? two pgood outputs (pwm and both ldos) ? overcurrent protection ? thermal overload protection ? internal 5v ldo regulator ? pb-free plus anneal available (rohs compliant) applications ? general purpose ? wlan cards-pcmcia, card bus32, minipci cards- compact flash cards ? hand-held instruments pinout ISL8501 (24 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8501irz* 85 01irz -40 to +85 24 ld 4x4 qfn l24.4x4d *add ?-t? suffix for tape and reel note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. cc1 pg_pwm fb_pwm comp ss en cc2 pg_ldo en_ldo2 en_ldo1 gnd vcc fb_ldo1 vout1 vin_ldo2 vin_ldo1 vout2 fb_ldo2 vin vin phase phase boot pvcc 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 gnd 25 data sheet july 12, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6500.1 july 12, 2007 typical application schematics figure 1. vin range from 4.5v to 5.5v 5v ISL8501 vin c8 ldo2 1.8v r7 r8 ldo1 enable fb_ldo2 ldo2 enable ldo pgood en_ldo2 pg_ldo c12 c4 cc2 cc1 vcc gnd c2 r4 vout2 r5 c6 ldo1 1.2v comp fb_pwm en_ldo1 c14 pvcc c9 pwm pgood pg_pwm c5 ss pwm enable en r1 r3 r2 c1 c3 vout c7 vout1 vin_ldo1 vin_ldo2 vin c11 l +3.3v phase boot vout1 c10 ~2.5v unregulated 301 100pf 10k 10pf 10nf 20k 2.21k 0.033 f 0.1 f r6 5.11k 5.11k 22 f 10 f 22 f 5.11k 2.55k 0.1 f 1 f 0.1 f d 10 h b340lb 100 f 10 f fb_ldo1 ISL8501
3 fn6500.1 july 12, 2007 figure 2. v in range from 6v to 25v typical application schematics (continued) 5v ISL8501 vin c8 ldo2 1.8v r7 r8 ldo1 enable fb_ldo2 ldo2 enable ldo pgood en_ldo2 pg_ldo c12 c4 cc2 cc1 vcc gnd c2 r4 vout2 r5 c6 ldo1 1.2v comp fb_pwm en_ldo1 c14 pvcc c9 pwm pgood pg_pwm c5 ss pwm enable en r1 r3 r2 c1 c3 vout c7 vout1 vin_ldo1 vin_ldo2 c11 l phase boot vout1 c10 301 100pf 10k 10pf 10nf 20k 2.21k 0.033 f 0.1 f r6 5.11k 5.11k 22 f 10 f 22 f 5.11k 2.55k 0.1 f 1 f 0.1 f d 10 h b340lb 100 f 10uf fb_ldo1 ISL8501
4 fn6500.1 july 12, 2007 functional block diagram + - ldo1 phase (x2) vin (x2) ramp generator oscillator ldo 0.6v oc ea pwm por en_ldo1 en_ldo2 gnd vin_ldo1 vout1 cc1 gm fb_ldo1 reference + - ldo2 vin_ldo2 vout2 cc2 gm fb_ldo2 pg_ldo pg_pwm pvcc gate drive boot oc monitor + - comp + - fb vin pvcc control soft-start 30 a en monitor voltage vcc monitor fault monitor vcc power-on reset monitor vin_ldo1 vin_ldo2 -15% comp. -15% comp. thermal monitor +150 o c ref control ldo2 logic por fault ref control ldo1 logic por fault ss vin ISL8501
5 fn6500.1 july 12, 2007 absolute maxi mum ratings (note 1) thermal information vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +26v vin_ldox to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v boot to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v phase to boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +0.3v vcc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vout, ldo1, ldo2 to gnd . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v fb_pwm, fb_ldox to gnd. . . . . . . . . . . . . . . . . . . . . -0.3v to +6v pg_pwm, pg_ldox to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to +6v en, en_ldox to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v cc1, cc2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vcc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2). . . . . . . . . . 36 5 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c junction temperature range. . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. *an accidental short between vcc and gnd may cause excessive heating and permanent damage to the device. notes: 1. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 2. for jc , the ?case temp? location is the center of the exposed meta l pad on the package underside. see tech brief tb379 for details. electrical specifications unless otherwise noted, all parameter limits ar e guaranteed over the recommended operating conditions and the typical specifications are me asured at the following conditions: t a = -40c to +85c (note 7), v in = 6v to 25v, unless otherwise noted. typical values are at t a = +25c. parameter symbol test conditions min typ max units supply voltage vin voltage range vin 6 25 v vin connected to vcc 4.5 5.0 5.5 v vin_ldox voltage range (note 6) 1.8 4.6 v vin operating supply current i op (note 3) 2.5 3.5 ma vin shutdown supply current i sd en = en_ldox = gnd 70 100 a power-on reset vcc por threshold rising edge 4.25 4.40 4.50 v hysteresis 260 mv vin_ldox por threshold rising edge 1.2 v hysteresis 200 mv internal vcc ldo vcc output voltage range vin = 6v to 25v, i vcc = 0ma to 50ma 4.5 5.00 5.5 v reference reference voltage v fb vin = 6v to 25v, i ref = 0 0.590 0.6 0.609 v standard buck pwm regulator fb_pwm line regulation iout = 0ma, vin = 6v to 25v -0.5 0.5 % fb_pwm leakage current vfb = 0.6v 0 50 100 na oscillator and pwm modulator nominal switching frequency f sw t a = -40c to +85c, vcc = 5v 450 500 550 khz modulator gain a mod vin = 12v (amod = 10/vin) 0.73 0.86 0.99 v/v peak-to-peak sawtooth amplitude v ramp vin = 12v (vpp = vin/10) 1.2 v pwm ramp offset voltage v offset 0.70 0.8 0.91 v maximum duty cycle dc max comp >4v 80 83 % error amplifier open-loop gain 88 db gain bandwidth product gbwp 15 mhz slew rate sr comp = 10pf 5 v/ s ISL8501
6 fn6500.1 july 12, 2007 enable section en threshold rising edge 1.2 1.7 2.2 v hysteresis 350 mv en_ldox logic input threshold rising edge 1.2 1.7 2.2 v hysteresis 400 mv en_ldox logic input current -1 1 a fault protection thermal shutdown temperature t sd rising threshold 150 c t hys hysteresis 15 c pwm uv trip level v uv referred to nominal vout 65 70 75 % pwm uvp propagation delay 360 ns pwm ocp threshold (note 4) 1.85 2.7 3.00 a ocp blanking time 150 ns power good pg_pwm trip level referred to nominal vout falling edge, 15mv hysteresis 84 88 92 % rising edge, 15mv hysteresis 107 110 113 % pg_pwm and pg_ldox propagation delay 160 ns pg_pwm low voltage isink = 4ma 0.3 v pg_pwm leakage current v pg_pwm = 5v, v fb_pwm = 600mv -1 1 a pg_ldox trip level referred to nominal vout falling edge, 15mv hysteresis 81 85 88 % pg_ldox low voltage isink = 4ma 0.3 v pg_ldox leakage current v pg_ldox = 5v, v fb_ldox = 600mv -1 1 a soft-start section soft-start threshold to enable buck 0.8 1.0 1.2 v soft-start threshold to enable pg 2.8 2.95 3.1 v soft-start voltage high 3.3 v soft-start charging current 25 30 35 a soft-start pull-down v ss = 3.0v 25 ma power mosfet r ds(on) iout = 100ma 120 350 m ldox fb_ldox voltage accuracy iout = 10ma -1.5 1.5 % fb leakage current vfb = 0.6v -200 -80 na output current limit 550 800 1000 ma dropout voltage iout = 450ma, vout > 2v (note 5) 150 300 mv fb_ldox line regulation iout = 0ma, vin_ldo1 = 2.0 ~4.6v -0.6 0.6 %/v fb_ldox load regulation iout = 10ma to 500ma 0.5 % notes: 3. test condition: v in = 15v, fb forced above regulation point (0.6v), no switch ing, and power mosfet gate charging current not included. 4. limits established by characterization and are not production tested. 5. the dropout voltage is defined as minimum amount vin must exceed a desired vout operating point. v ldo = v in_ldo - v out . 6. the input voltage vcc must be higher than vin_ldo or the ldo will not function. 7. specifications at -40c to +85c are guar anteed by +25c test with margin limits. electrical specifications unless otherwise noted, all parameter limits ar e guaranteed over the recommended operating conditions and the typical specifications are me asured at the following conditions: t a = -40c to +85c (note 7), v in = 6v to 25v, unless otherwise noted. typical values are at t a = +25c. (continued) parameter symbol test conditions min typ max units ISL8501
7 fn6500.1 july 12, 2007 pin descriptions vin the input supply for the pwm regulator power stage and the source for the internal linear regulator that provides bias for the ic. place a ceramic capacitor from vin to gnd, close to the ic for decoupling (typical 1 f). pvcc connect this pin to vcc. gnd ground connect for the ic and thermal relief for the package. the exposed pad must be connected to gnd and soldered to the pcb. all voltage levels are measured with respect to this pin. vcc internal 5v linear regulator out put provides bias to all the internal control logic. the ISL8501 may be powered directly from a 5v (10%) supply at this pin. when used as a 5v supply input, this pin must be externally connected to vin. the vcc pin must always be decoupled to gnd with a ceramic bypass capacitor (minimum 1 f) located close to the pin. fb and comp the standard buck regulator employs a single voltage control loop. fb is the negative input to the voltage loop error amplifier. comp is the output of the error amplifier. the output voltage is set by an external resistor divider connected to fb. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. connecting an ac network across comp and fb provide loop compensation to the amplifier. in addition, the pwm regulator power good and under- voltage protection circuitry use fb to monitor the regulator output voltage. phase switch node connections to internal power mosfet source, external output inductor, and external diode cathode. boot floating bootstrap supply pin for the power mosfet gate driver. the bootstrap capacitor provides the necessary charge to turn and hold on the internal n-channel mosfet. connect an external capaci tor from this pin to phase. en pwm controller enable input. the pwm converter and ldo's outputs are held off when the pin is pulled to ground. when the voltage on this pin rises above 1.7v, the chip is enabled. ss program pin for soft-start duration. a regulated 30 a pull-up current source charges a capacitor connected from the pin to gnd. the output voltage of the converter follows the ramping voltage on the ss pin. vin_ldo1, vin_ldo2 input voltage pin for each ldo. vout1, vout2 ldo output pins. bypass with a minimum of 2.2 f, low esr capacitor to gnd for stable operation. fb_ldo1, fb_ldo2 used to set the output of ldo with the proper selection of resistor divider. the resistors should be selected to provide a minimum current of 200na load for the ldo. cc1, cc2 compensation capacitor connection for each ldo. connect a 0.033 f capacitor from each pin to ground. en_ldo1, en_ldo2 these pins are threshold-sensitive enable inputs for the individual ldos. held low, this pin disables the respective ldo. pg_pwm pwm converter power good output. open drain logic output that is pulled to ground when the output voltage is outside regulation limits. connect a 100k resistor from this pin to vcc. pin is low when the buck regulator output voltage is not within 10% of the respective nominal voltage, or during the soft-start interval. pin is high impedance when the output is within regulation. pg_ldo combined ldo power good output. connect a 100k resistor from this pin to vcc. table 1. input supply configuration input pin configuration 6v to 25v connect the input supply to the vin pin only. the vcc pin will provide a 5v output from the internal linear regulator. 5v 10% connect the input supply to the vin and vcc pins. ISL8501
8 fn6500.1 july 12, 2007 typical performance curves circuit of figure 2. v in = 12v, vin_ldo1 = vin_ldo2 = v out1 = 3.3v, i out1 = 1a, v ldo1 = 1.2v, i ldo1 = 450ma, v ldo2 = 1.8v, i ldo2 = 450ma, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. figure 3. efficiency vs load, v in = 7v figure 4. efficiency vs load, v in = 12v figure 5. efficiency vs load, v in = 25v figure 6. v out regulation vs load, 500khz 1.2v out figure 7. v out regulation vs load, 500khz 1.2v out figure 8. v out regulation vs load, 500khz 1.8v out 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out 1.2v out 1.8v out 2.5v out 3.3v out 5.0v out 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out 1.8v out 1.2v out 2.5v out 3.3v out 5.0v out 0 10 20 30 40 50 60 70 80 90 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out 1.8v out 1.2v out 2.5v out 3.3v out 5.0v out 1.212 1.213 1.214 1.215 1.216 1.217 1.218 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in 1.505 1.506 1.506 1.507 1.507 1.508 1.508 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in 1.806 1.807 1.807 1.808 1.808 1.809 1.809 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in ISL8501
9 fn6500.1 july 12, 2007 figure 9. v out regulation vs load, 500khz 2.5v out figure 10. v out regulation vs load, 500khz 3.3v out figure 11. v out regulation vs load, 5v out figure 12. power dissipation vs load, 3.3v out figure 13. input power vs v in , v out = 3.3v figure 14. output voltage regulation vs v in typical performance curves circuit of figure 2. v in = 12v, vin_ldo1 = vin_ldo2 = v out1 = 3.3v, i out1 = 1a, v ldo1 = 1.2v, i ldo1 = 450ma, v ldo2 = 1.8v, i ldo2 = 450ma, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. (continued) 2.500 2.501 2.501 2.502 2.502 2.503 2.503 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in 3.300 3.303 3.305 3.308 3.310 3.313 3.315 3.318 3.320 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in 5.005 5.006 5.007 5.008 5.009 5.010 5.011 5.012 5.013 5.014 5.015 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 12v in 25v in 7v in 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 12v in 25v in 7v in 0.00 0.02 0.04 0.06 0.08 0.10 0.12 5 7 9 1113151719212325 input voltage (v) input power (w) no load 3.310 3.312 3.314 3.316 3.318 3.320 5 7 9 11 13151719212325 output voltage (v) input voltage (v) no load 2a load 1a load ISL8501
10 fn6500.1 july 12, 2007 figure 15. v cc load regulation figure 16. v cc regulation with v in figure 17. ldo1 vs load, 500khz, vin_ldo1 = 3.3v figure 18. ldo2 vs load, 500khz vin_ldo2 = 3.3v figure 19. steady state operation at no load, 5s/ div figure 20. steady state operation at full load, 1s/div typical performance curves circuit of figure 2. v in = 12v, vin_ldo1 = vin_ldo2 = v out1 = 3.3v, i out1 = 1a, v ldo1 = 1.2v, i ldo1 = 450ma, v ldo2 = 1.8v, i ldo2 = 450ma, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. (continued) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 0 50 100 150 200 i v cc (ma) v cc (v) 0 1 2 3 4 5 6 0 5 10 15 20 25 30 v in (v) v cc (v) no load 50ma load 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 0 100 200 300 400 500 600 700 output load (ma) output voltage (v) 12v in 25v in 7v in 1.70 1.72 1.74 1.76 1.78 1.80 1.82 1.84 1.86 1.88 1.90 0 100 200 300 400 500 600 700 output load (ma) output voltage (v) 12v in 25v in 7v in phase 10v/div vout1 ripple 20mv/div il 0.2a/div ldo1 ripple 20mv/div ldo2 ripple 20mv/div phase 10v/div vout1 ripple 20mv/div il 1a/div ldo1 ripple 20mv/div ldo2 ripple 20mv/div ISL8501
11 fn6500.1 july 12, 2007 figure 21. load transient, 200s/div figure 22. soft-start at no load, 500s/div figure 23. soft-start at full load, 500s/div f igure 24. soft-start at full load, 500s/div figure 25. shut down circuit at full load, 100s/div figure 26. shut down circu it at full load, 100s/div typical performance curves circuit of figure 2. v in = 12v, vin_ldo1 = vin_ldo2 = v out1 = 3.3v, i out1 = 1a, v ldo1 = 1.2v, i ldo1 = 450ma, v ldo2 = 1.8v, i ldo2 = 450ma, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. (continued) phase 10v/div vout1 ripple 100mv/div il 1a/div ldo1 ripple 20mv/div ldo2 ripple 20mv/div en 5v/div vout1 2v/div ss 2v/div pg_pwm 5v/div ldo2 1v/div ldo1 1v/div en 5v/div vout1 2v/div pg_pwm 2v/div il 1a/div ss 2v/div en 5v/div ldo1 2v/div pg_ldo 5v/div ldo2 2v/div en 5v/div vout1 2v/div pg_pwm 5v/div il 1a/div en 5v/div ldo1 1v/div pg_ldo 5v/div ldo2 1v/div ISL8501
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6500.1 july 12, 2007 figure 27. output short circuit, 5s/div figure 28. output short circuit recovery, 200s/div figure 29. ldo1 short circuit and recovery, 200s/div figure 30. ldo2 short circuit and recovery, 200s/div typical performance curves circuit of figure 2. v in = 12v, vin_ldo1 = vin_ldo2 = v out1 = 3.3v, i out1 = 1a, v ldo1 = 1.2v, i ldo1 = 450ma, v ldo2 = 1.8v, i ldo2 = 450ma, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. (continued) phase 10v/div vout1 2v/div pg_pwm il 1a/div vout1 1v/div il 2a/div pg_pwm 5v/div pg_ldo 5v/div ldo1 500mv/div ildo1 1a/div pg_ldo 5v/div ldo2 1v/div ildo2 1a/div ISL8501
13 fn6500.1 july 12, 2007 detailed description the ISL8501 combines a standard buck pwm controller with an integrated switching mosfet and two low dropout (ldo) linear regulators with internal pass devices. the buck controller drives an internal n-channel mosfet and requires an external diode to deliver load current up to 1a. a schottky diode is recommended for improved efficiency and performance over a standard diode. the standard buck regulator can operate from either an unregulated dc source, such as a battery, with a voltage ranging from +6.0v to +25v, or from a regulated system rail of +5v. when operating from +6v or greater, the controller is biased from an internal +5v ldo voltage regulator. the converter output is regulated down to 0.6v from either input source. each ldo linear regulator can source up to 50 0ma continuous output current with +2v or greater input suppl y and +1.0v or higher output voltage. these features make the ISL8501 ideally suited for fpga and wireless chipset power applications. the pwm control loop uses a si ngle output voltage loop with input voltage feed forward which simplifies feedback loop compensation and rejects input voltage variation. external feedback loop compensation allows flexibility in output filter component selection. the regulator switches at a fixed 500khz. the buck regulator and ldos are provided with independent current limits. the current li mit in the buck regulator is achieved by monitoring the drain-to-source voltage drop of the internal switching power mosfet. the current limit threshold is internally set at 2a. the part also features undervoltage protection by latching the switching mosfet driver to the off state during an overcurrent, when the output voltage is lower than 70% of the regulated output. this helps minimize power dissipation during a short-circuit condition. due to only the switching power mosfet integration, there is no overvoltage protection feature for this part. the ISL8501 monitors and controls the pass transistor?s gate voltage to limit the output current. the current limits for both ldos is 800ma typical. ne ither ldo has overvoltage or undervoltage protection. when the current limit in either output is reached, the output no longer regulates the voltage, but regulates the current to th e value of the current limit. +5v internal bias supply (vcc) voltage applied to the vin pin with respect to gnd is regulated to +5v dc by an internal ldo regulator. the output of the ldo, vcc, is t he bias voltage used by all the internal control and protection circuitry. the vcc pin requires a ceramic capacitor connected to gnd. the capacitor serves to stabilize the ldo and to decouple load transients. the input voltage range for the ISL8501 is specified as +6v to +25v or +5v 10%. in the case of an unregulated supply case, the power supply is connected to vin only. once enabled, the linear regulator will turn-on and rise to +5v on vcc. in the +5v supply case, the vcc and vin pins must be tied together to bypass the ldo. the external decoupling capacitor is still required in this mode. do not short vcc to gnd. operation initialization the power-on reset circuitry and enable inputs prevent false startup of the pwm regulator and ldo outputs. once all the input criteria are met, the co ntroller soft-starts the output voltage to the programmed level. power-on reset and undervoltage lockout the pwm portion of the ISL8501 automatically initializes upon receipt of input power. the power-on reset (por) function continually monitors the vcc and pvcc voltages. while both are below their por thresholds, the controller inhibits switching of the internal power mosfet. once exceeded, the controller initializes the internal soft-start circuitry. if either input supply drops below their falling por threshold during soft-start or operation, the buck regulator latches off. independent ldo supply inputs (vin_ldo1 and vin_ldo2) allow flexibility in partitioni ng linear regulator power. power supplies connected to either ldo supply input must exceed the undervoltage lockout (uvlo) threshold before that ldo is initialized. if the input supply drops below the falling uvlo threshold during operation, the low dropout voltage regulator latches off. enable and disable all internal power devices are held in a high-impedance state, which ensures they remain off while in shutdown mode. typically the enable input for a specific output is toggled high after the input supply to that regulator is active and the internal ldo has exceeded its por threshold. the en pin enables the buck controller portion of the ISL8501. when the voltage on the en pin exceeds the por rising threshold, the controller initiates the soft-start function for the pwm regulator. if the voltage on the en pin drops below the por falling threshold, the buck regulator shuts down. individual ldo enable inputs (en_ldo1 and en_ldo2) allow independent control of each regulator. make sure en is on, when the voltage on either pin exceeds the por rising threshold, linear regulator oper ation is initiated for that controller. if the voltage then drops below the hysteresis level for the enable pin, the ldo shuts down. pulling the en low simultaneously puts all outputs into shutdown mode, and supply current drops to 10 a typical. soft-start once the input supply latch and enable threshold are met, the soft-start function is initia lized. the soft-start circuitry begins sourcing 30 a, from an internal current source, which ISL8501
14 fn6500.1 july 12, 2007 charges the external soft-start capacitor. the voltage on ss begins ramping linearly from ground until the voltage across the soft-start capacitor reache s 3.0v. this linear ramp is applied to the non-inverting input of the internal error amplifier and overrides the nominal 0.6v reference. the output voltage reaches its regulation value when the soft- start capacitor voltage reaches 1.6v. connect a capacitor from ss pin to ground. this capacitor, along with an internal 30 a current source sets the so ft-start interval of the converter, t ss . upon disable, ss pin voltage will discharge to zero voltage. power good pg_pwm is an open-drain output of a window comparator that continuously monitors th e buck regulator output voltage. pg_pwm is actively held low when en is low and during the buck regulator soft-start period. after the soft-start period terminates, pg_pwm becomes high impedance as long as the output voltage is within 10% of the nominal regulation voltage set by fb_pwm. when vout drops 10% below or rises 10% above the nominal regulation voltage, the ISL8501 pulls pg_pwm low. any fault condition forces pg_pwm low until the fault condition is cleared by attempts to soft-start. for logic level output voltages, connect an external pull-up resistor between pg_pwm and vcc. a 100k resistor works well in mo st applications. note that the pg_pwm window detector is completely independent of the undervoltage protection fault detectors and the state of ldo1 and ldo2 outputs. pg_ldo is an open drain pull-down nmos output that will sink 1ma at 0.3v max. pg_ldo monitors both ldo1 and ldo2 output. it goes to the active low state if either ldo output is below regulation by a value greater than 15%. when the one of the ldo is disabled, the pg_ldo switch to only monitor the active ldo output. output voltage selection all three regulator output voltages can be programmed using external resistor dividers that scale the voltage feedback relative to the internal reference voltage. the scaled voltage is fed back to the inverting input of the error amplifier. refer to figure 3. the output voltage programming resistor, r 2 , will depend on the value chosen for the feedback resistor, r 1 , and the desired output voltage, v out , of the regulator. see equation 1. the value for the feedback resistor is typically between 1k and 10k . if the output voltage desired is 0.6v, then r 2 is left unpopulated. the buck output can be program as high as 20v. proper heatsinking must be provided to insure that the junction temperature do not exceed +125c. when the output is set greater than 3.6v, it is recommended to pre-load at least 1ma and make sure that the input rise time is >> faster than the vo ut1 rise time. this allows the boot capacitor adequate time to charge for proper operation. protection features the ISL8501 limits current in all on-chip power devices to limit on-chip power dissipation. overcurrent limits on all three regulators protect internal power devices from excessive thermal damage. undervoltage protection circuitry on the buck regulator provides a second layer of protection for the internal power device under high current conditions. buck regulator overcurrent protection during the pwm on-time, the current through the internal switching mosfet is sampled and scaled through an internal pilot device. the sampled current is compared to a nominal 2a overcurrent limit. if the sampled current exceeds the overcurrent limit reference le vel, an internal overcurrent fault counter is set to 1 and an internal flag is set. the internal power mosfet is immediately turned off and will not be turned on again until the next switching cycle. the protection circuitry continue s to monitor the current and turns off the internal mosfet as described. if the over- current condition persists for four sequential clock cycles, the over-current fault counter overflows indicating an overcurrent fault condition exists . the regulator is shut down and power good goes low. if the overcurrent condition clears prior to the counter reaching four consecutive cycles, the internal flag and counter are reset. the protection circuitry atte mpts to recover from the overcurrent condition after wa iting 4 soft-start cycles. the internal overcurrent flag and counter are reset. a normal soft-start cycle is attempted and normal operat ion continues if the fault condition has cleared. if the overcurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. c ss f [] 50 t ss s [] ? = (eq. 1) r2 r1 0.6v ? v out 0.6v ? ---------------------------------- = (eq. 2) r1 r2 0.6v ea reference + - v out figure 31. external resistor divider ISL8501
15 fn6500.1 july 12, 2007 ldo current limit the ISL8501 monitors and controls the pass transistor?s gate voltage to limit output current. the current limit for both ldo1 and ldo2 is 700ma typical. the output can be shorted to ground without dam aging the part due to the current limit and thermal protection features. undervoltage protection if the voltage detected on the buck regulator fb pin falls 15% below the internal reference voltage, the undervoltage fault condition flag is set. the fault protection circuitry checks the overcurrent flag. if the overcu rrent flag is set, the fault monitor latches off the internal power mosfet. the regulator will not restart until either a por restart or the en pin is cycled. if the overcurrent flag is not set, an internal undervoltage counter is set to 1. the fault controller continues to monitor the fb pin for 4 clock cycles. if the fault condition persists, the regulator is shutdown. the controller enters a recovery mode similar to the overcurrent hiccup mode. no action is taken for 4 soft-start cycles and the internal undervoltage counter and fault condition flag are reset. a normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. if the undervoltage counter overflows during soft-start, the converter is shut down and this hiccup mode operation repeats. under-voltage protection only applies to the buck regulator output, the two ldo outputs do not have undervoltage protection. thermal overload protection thermal overload protection limits total power dissipation in the ISL8501. there are three s ensors on the chip to monitor the junction temperature of the internal ldo, pwm switching power n-channel mosfet, and ldo pass transistors. when the junction temperature (t j ) of any of the three sensors exceeds +150c, the thermal sensor sends a signal to the fault monitor. the fault monitor commands the buck regulator to shut down and the ldos to turn off their pass transistors. the buck regulator soft-starts and the ldo pass transistors turn on again after the ic?s junction temperature cools by +20c. the buck regulator experiences hiccup mode operation and the ldos a pulsed output during continuous thermal overload conditions. for c ontinuous operation, do not exceed the +125c junction temperature rating. low dropout regulators each regulator consists of a 0. 6v reference, e rror amplifier, mosfet driver, p-channel pass transistor, and dual-mode comparator. the voltage is set by means of an external resistor divider on the fb_ldox pins. the 0.6v band gap reference is connected to the error amplifier?s inverting input. the error amplifier compares th is reference to the selected feedback voltage and amplifies the difference. the mosfet driver reads the error signal and applies the appropriate drive to the p-channel pass transistor. if the feedback voltage is lower than the reference voltage, the pass transistor gate is pulled lower, allowing more current to pass and increasing the output voltage . if the feedback voltage is higher than the reference voltage, the pass transistor gate is driven higher, allowing less current to pass to the output. internal p-channel pass transistor both the ldo regulators in the ISL8501 feature a typical 0.33 r ds(on) p-channel mosfet pass transistor. this provides several advantages over similar designs using pnp bipolar pass transistors. the p-channel mosfet requires no base drive, which reduces quiescent current considerably. pnp based regulators waste considerable current in drop out when the pass transistor saturates. they also use high base drive currents under large loads. the ISL8501 does not have these drawbacks. integrator circuitry the ISL8501 uses external compensation capacitors for minimizing load and line regulation errors and for lowering output noise. when the output voltage shifts due to varying load current or input voltage, the integrator capacitor voltage is raised or lowered to compen sate for the systematic offset at the error amplifier. compensation is limited to 5% to minimize transient overshoot when the device goes out of dropout, current limit, or thermal shutdown. place a 33nf capacitor to gnd from cc1 and cc2. application guidelines operating frequency the ISL8501 operates at a fixed switching frequency of 500khz. ldo regulator capacitor selection capacitors are required at the ISL8501 ldo regulators? input and output for stable oper ation over the entire load range and the full temperature r ange. use >1f capacitor at the input of ldo regulators, vin_ldo pins. the input capacitor lowers the source impedance of the input supply. larger capacitor values and lower esr provides better psrr and line transient response. the input capacitor must be located at a distance of not more then 0.5 inches from the vin_ldo pins of the ic and returned to a clean analog ground. any good quality ceramic capacitor can be used as an input capacitor. the output capacitors used in ldo regulators are used to provide dynamic load current. the amount of capacitance and type of capacitor should be chosen with this criteria in mind. the output capacitor selected must meet the requirements of minimum amount of capacitance and esr for both ldos. the ISL8501 is specifically designed to work with small ceramic output capaci tors. the output capacitor?s esr affects stability and output noise. use an output capacitor with an esr of 50m or less to insure stability and ISL8501
16 fn6500.1 july 12, 2007 optimum transient response. for stable operation, a ceramic capacitor, with a minimum value of 10f, is recommended for both ldo outputs. there is no upper limit to the output capacitor value. larger capacitor can reduce noise and improve load transient response, stability and psrr. the output capacitor should be located very close to v out pins to minimize impact of pc board inductances and the other end of the capacitor should be returned to a clean analog ground. buck regulator output capacitor selection an output capacitor is required to filter the inductor current and supply the load transi ent current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. embedded processor systems are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient an d slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements, rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr ava ilable in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to hi gh slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. the recommended i is 30% of the maximum output current. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the ISL8501 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor cu rrent from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. rectifier selection current circulates from ground to the junction of the mosfet and the inductor when the high-side switch is off. as a consequence, the polarity of the switching node is negative with respect to ground. this voltage is approximately -0.5v (a schott ky diode drop) during the off time. the rectifier's rated reverse breakdown voltage must be at least equal to the maxi mum input voltage, preferably with a 20% derating factor. the power dissipation is: where v d is the voltage of the sc hottky diode = 0.5v to 0.7v input capacitor selection use a mix of input bypass capaci tors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the switching mosfet turns on. place the small ceramic capacitors physically close to the mosfet vin pins (switching mosfet drain) and the schottky diode anode. i = v in - v out fs x l v out v in v out = i x esr x (eq. 3) t rise = l x i tran v in - v out t fall = l x i tran v out (eq. 4) p d w [] i out v d 1 v out v in --------------- - ? ?? ?? ?? ?? = (eq. 5) ISL8501
17 fn6500.1 july 12, 2007 the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. for most cases, the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. the maximum rms current required by the regulator may be closely approximated through the equation 6: for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised wih regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. feedback compensation figure 2 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the ISL8501) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. the following equations relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 4 , c 1 , c 2 , and c 3 ) in figure 2. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place1 st zero below filter?s double pole (~75% f lc ). 3. place 2nd zero at filter?s double pole. 4. place 1st pole at the esr zero. 5. place 2nd pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin - repeat if necessary. compensation break frequency equations figure 3 shows an asymptotic pl ot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 3. using the guidelines from ?modulator break frequency equations? on page 17 should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 33 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. i rms max v out v in ------------- - i out max 2 1 12 ------ v in v out ? lf s ---------------------------- - v out v in ------------- - ?? ?? 2 + ?? ?? = (eq. 6) f lc 1 2 x l o x c o ------------------------------------------ - = f esr 1 2 x esr x c o ------------------------------------------- - = (eq. 7) f z1 1 2 x r 4 x c 2 ------------------------------------ = f z2 1 2 x r 1 r 3 + () x c 1 ------------------------------------------------------ - = f p1 1 2 x r 4 x c 3 x c 2 c 3 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = f p2 1 2 x r 3 x c 1 ------------------------------------ = (eq. 8) figure 32. voltage-mode buck converter compensation design and output voltage selection v ddq reference l o c o esr v in v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 4 c 1 c 3 c 2 comp v ddq fb z fb ISL8501 z in comparator driver detailed compensation components phase v e/a + - + - z in osc r 2 ISL8501
18 fn6500.1 july 12, 2007 the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. a more detailed explanation of voltage mode control of a buck regulator can be found in tech brief tb417, titled ?designing stable compensation networks for single phase voltage mode buck regulators.? layout considerations layout is very important in high frequency switching converter design. with power devices switching efficiently at 500khz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, ra diate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes these voltage spikes. as an example, consider the turn-off transition of the upper mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the schottky diode. any parasitic inductance in the swit ched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide traces minimi zes the magnitude of voltage spikes. there are two sets of critic al components in the ISL8501 switching converter. the switch ing components are the most critical because they switch large amounts of energy, and therefore tend to generate larg e amounts of noise. next are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 34 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer (usually a middle layer of the pc board) for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. in order to dissipate heat generated by the internal ldo and mosfet, the ground pad, pin 29, should be connected to the internal ground plane through at least four vias. this allows the heat to move away from the ic and also ties the pad to the ground plane through a low impedance path. the switching components should be placed close to the ISL8501 first. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper and lower mosfets and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors should be located as close as possible to the fb pin with vias tied straight to the ground plane as required. 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 20log f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / v osc ) modulator gain (r 2 /r 1 ) figure 33. asymptotic bode plot of converter gain closed loop gain figure 34. printed circuit board power planes and islands vin pvcc ISL8501 vcc phase pgnd comp fb gnd pad r 4 r 3 c 3 r 1 c 1 c 2 r 2 c out1 v out1 c in v in l c bp2 r bp c bp1 5v island on power plane layer island on circuit and/or power plane layer via connection to ground plane key load d ISL8501
19 fn6500.1 july 12, 2007 ISL8501 package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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